There is considerable interest in heterostructure devices involving greater epitaxial layer thickness and greater lattice misfit than present technology will allow. For example, it has long been recognized that germanium-silicon alloy Ge.sub.x Si.sub.l-x grown on silicon substrates would permit a variety of optoelectronic devices, such as LEDs, marrying the electronic processing technology of silicon VLSI circuits with the optical component technology available in direct band semiconductors. Indeed, it has been proposed that an intermediate epitaxial layer of germanium-silicon alloy would permit the epitaxial deposition of gallium arsenide overlying a silicon substrate and thus permit a variety of new optoelectronic devices using silicon electronic components and gallium arsenide optical components. However, despite the widely recognized potential advantages of such combined structures and despite substantial efforts to develop them, their practical utility has been limited by high defect densities in heterostructure layers grown on silicon substrates.
Dislocation defects partition an otherwise monolithic crystal structure and introduce unwanted and abrupt changes in electrical and optical properties. Dislocation defects arise in efforts to epitaxially grow one kind of crystalline material on a substrate of a different kind of material due to different crystal lattice sizes of the two materials. Dislocations from at the mismatched interface to relieve the misfit strain. Many of the misfit dislocations have vertical components, termed threading segments, which extend at a slant angle through any subsequent layers. Such threading defects in the active regions of semiconductor devices seriously degrade device performance.
A variety of approaches have been used to reduce dislocations with varying degrees of success. One approach is to limit the heterolayer to a thin layer of material that has a lattice crystal structure closely matching the substrate. Typically the lattice mismatch is within 1% and thickness of the layer is kept below a critical thickness for defect formation. In such structures, the substrate acts as a template for growth of the heterolayer which elastically conforms to the substrate temperature. While this approach eliminates dislocations in a number of structures, there are relatively few near lattice-matched systems with large energy band offers. Thus with this approach the design options for new devices are limited.
A second approach set forth in the copending application of E. A. Fitzgerald, Ser. No. 07/561,774 filed Aug. 2, 1990 new U.S. Pat. No. 5,158,907 utilizers heterolayers of greater thickness but limited lateral area. By making the thickness sufficiently large as compared with the lateral dimension, threading dislocations are permitted to exit the sides of layer. The upper surface is thus left substantially free of defects. This approach permits the fabrication of a variety of devices and circuits which can be made on limited area surfaces having an area of less than about 10,000 square micrometers.
A third approach is to deposit successive layers of germanium-silicon alloy on a silicon substrate, increasing the germanium content with each successive layer. The goal is to avoid dislocations by spreading the strain among successive layers. Unfortunately this approach has not worked. For example, it has been found that step grading 20% Ge over 2000 angstroms to produce pure Ge results in substantially the same high dislocation density as depositing pure Ge on Si. See J. M. Baribeau et al., 63 Journal of Applied Physics 5738 (1988). Applicants believe that this approach fails because at conventional growth temperatures--typically about 550.degree. C.--the initial layer of Si--Ge is almost entirely elastically strained. Thus when the next layer of Si--Ge with greater germanium content is applied, the mismatch between the two Si--Ge layers is nearly that between the initial Si--Ge layer and the Si substrate, resulting in high dislocation density. Accordingly, there is a need for a method of making large area, low defect heterostructures on silicon.